View ICS8430-51_316630.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Dual differential 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Maximum output frequency: 600MHz * Crystal input frequency range: 14MHz to 25MHz * VCO range: 200MHz to 700MHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 2.6ps (typical) * Cycle-to-cycle jitter: 17ps (typical) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8430-51 is a general purpose, dual output ,&6 Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockSTM Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8430-51 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 200MHz to 700MHz. With FOUT0 configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz crystal or reference clock. FOUT1 provides an additional divide by 16 and 180 phase shift. Output frequencies up to 600MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the ICS8430-51 make it an ideal clock generator for most clock tree applications.
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL1 OSC XTAL2 / 16 1
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL2 M4 M3 M2 M1 M0
32 31 30 29 28 27 26 25 0 M5 M6 M7 M8 N0 N1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
24 23 22
XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
ICS8430-51
21 20 19 18 17
PLL
PHASE DETECTOR MR /M /2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 CONFIGURATION INTERFACE LOGIC VCO 0 /N 1 /16
N2 VEE FOUT0 nFOUT0 FOUT1 nFOUT1
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430AY-51
www.icst.com/products/hiperclocks.html
1
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-51 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8430-51 support two input modes, programmable M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 M 350. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA
t
T1
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2
M, N
nP_LOAD
t
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8430AY-51
www.icst.com/products/hiperclocks.html
2
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Power Output Power Output Power Output Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 3, 28, 29, 30 31, 32, 4 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5, M6, M7, M0, M1, M2, M3, M4 M8 N0, N1 N2 VEE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Pulldown Determines output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Pullup Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/ LVTTL interface levels. Core power supply pin. Differential output for the synthesizer with shifted divide by 16. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted 17 MR Input Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift regiser 18 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge 19 S_DATA Input Pulldown of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. 20 S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. 21 VCCA Power Analog supply pin. Selects between the crystal oscillator or test clock as the PLL 22 XTAL_SEL Input Pullup reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. 24, 25 XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is 26 nP_LOAD Input Pulldown loaded into the M divider, and when data present at N2:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 27 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8430AY-51
www.icst.com/products/hiperclocks.html
3
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. X X L L L H
MR H L L L L L L
nP_LOAD X L H H H H
M X Data Data X X X X
N X Data Data X X X X
S_LOAD
L H X X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 200 202 204 206 * * 696 698 700 NOTE 1: These M divide 16MHz. M Divide 100 256 M8 0 128 M7 0 64 M6 1 32 M5 1 16 M4 0 8 M3 0 4 M2 1 2 M1 0 1 M0 0 1 0 1 * * 0 1 0
101 0 102 0 103 0 * * * * 348 1 349 1 350 1 values and the resulting
0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 * * * * * * * * * * 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 frequencies correspond to cr ystal or TEST_CLK
1 0 1 1 1 1 * * * * 1 0 1 0 1 1 input frequency of
8430AY-51
www.icst.com/products/hiperclocks.html
4
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FOUT0, nFOUT0 Output Frequency (MHz) Minimum Maximum 100 350 50 25 12.5 200 100 50 25 175 87.5 43.75 600 350 175 87.5
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divider Value 2 4 8 16 1 2 4 8
nFOUT0 FOUT0
nFOUT1 FOUT1
FIGURE 2. FOUTX TIMING DIAGRAM
8430AY-51
www.icst.com/products/hiperclocks.html
5
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 120 10 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH Input High Voltage Parameter TEST_CLK VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, MR, M0:M8, N0:N2, XTAL_SEL TEST_CLK VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N2, XTAL_SEL M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD M8, N2, XTAL_SEL, VCO_SEL M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD M8, N2, XTAL_SEL, VCO_SEL Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 1.3 0.8 Units V V V V
VIL
Input Low Voltage
IIH
Input High Current
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5
150 5
A A A
IIL
Input Low Current
-150 2.6 0.5
A V V
Output TEST; NOTE 1 High Voltage Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Outputs terminated with 50 to VCCO/2. VOH
8430AY-51
www.icst.com/products/hiperclocks.html
6
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Information" section, "3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL1, XTAL2; NOTE 1 Test Conditions Minimum 14 14 Typical Maximum 25 25 Units MHz MHz
S_CLOCK TBD MHz NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the 200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 M 400. Using the maximum frequency of 25MHz, valid values of M are 64 M 224.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 14 50 Test Conditions Minimum Typical Maximum 25 70 7 Units MHz pF Fundamental
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol FMAX Parameter Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise Time Output Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time Output Duty Cycle S_DATA to S_CLOCK S_CLOCK to S_LOAD 200 200 5 5 5 5 5 5 47 53 1 17 2.6 50 700 700 Test Conditions Minimum Typical Maximum 600 Units MHz ps ps ps ps ps ns ns ns ns ns ns % ms
tjit(cc) tjit(per) tsk(o)
tR tF
PLL Lock Time tLOCK Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430AY-51
www.icst.com/products/hiperclocks.html
7
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC , VCCA , VCCO = 2V
Qx
SCOPE
nFOUTx FOUTx
LVPECL
nQx
nFOUTy FOUTy
tsk(o)
VEE = -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH VREF VOL
nFOUTx FOUTx
tcycle
n
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
tjit(cc) = tcycle n -tcycle n+1
Histogram
Reference Point
(Trigger Edge)
1000 Cycles
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx FOUTx
Pulse Width t
PERIOD
odc =
t PW t PERIOD
odc & tPERIOD
8430AY-51
www.icst.com/products/hiperclocks.html
8
tcycle n+1
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8430-51 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10 F 10
FIGURE 3. POWER SUPPLY FILTERING
CRYSTAL INPUT
AND
OSCILLATOR INTERFACE
ppm performance over various parallel resonant crystals. Figure 4C shows the recommended tuning capacitance for various parallel resonant crystals.
The ICS8430-51 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. A 16MHz crystal divided by 16 before being sent to the phase detector provides the reference frequency. The oscillator is a series resonant, multi-vibrator type design. This design provides better stability and eliminates the need for large on chip capacitors. Though a series resonant crystal is preferred, a parallel resonant crystal can be used. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. A few hundred ppm translates to KHz inaccuracy. In general computing applications this level of inaccuracy is irrelevant. If better ppm accuracy is required, an external capacitor can be added to a parallel resonant crystal in series to pin 24. Figure 4A shows how to interface with a crystal. Figures 4A, 4B, and 4C show various crystal parameters which are recommended only as guidelines. Figure 4A shows how to interface a capacitor with a parallel resonant crystal. Figure 3B shows the capacitor value needed for the optimum FIGURE 4B. Recommended tuning capacitance for various parallel resonant crystals.
60 Series Capacitor, C1 (pF) 50 40 30 20 24.000 10 0 14 15 16 17 18 19 20 21 22 23 24 25 Crystal Frequency (MHz) 15.000 16.667 19.440 20.000 14.318
ICS8430-51
XTAL2
(Pin 25, LQFP)
XTAL1
FIGURE 4A. CRYSTAL INTERFACE
FIGURE 4C. Recommended tuning capacitance for various parallel resonant crystals.
100 80 60 40 20 0 -20 0 -40 -60 -80 -100
Frequency Accuracy (ppm)
10
20
30
Optional
(Pin 24, LQFP)
40
50
60
19.44MHz
Series Capacitor, C1 (pF)
16MHz 15.00MHz
8430AY-51
www.icst.com/products/hiperclocks.html
9
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
Zo = 50 FOUT
Zo = 50 5 2 Zo FIN Zo = 50
3.3V 5 2 Zo Zo = 50 FIN Zo = 50 3 2 Zo
Zo = 50 50
Zo = 50 50 VCC - 2V
FOUT
Zo = 50 3 2 Zo
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 5A. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8430-51 layout example used in this layout guideline is shown in Figure 6A. The ICS8430-51 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
32 31 30 29 28 27 26 25
U1
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL2
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 GND
1 2 3 4 5 6 7 8
M5 M6 M7 M8 N0 N1 N2 GND
VDD FOUT FOUTN
9 10 11 12 13 14 15 16
8430-01
TEST
VDD
C14 0.1u
FIGURE 6A. SCHEMATIC
8430AY-51
RTT
C15 0.1u
FIGURE 5B. LVPECL OUTPUT TERMINATION
X1
R7 VDD 10
XTAL1 REF_IN nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
24 23 22 21 20 19 18 17
C11 0.01u REF_IN XTAL_SEL S_LOAD S_DATA S_CLOCK MR
C16 22u
Termination A
VDD
Termination B (Not shown in the layout)
IN+ IN-
R1 125 Zo = 50 Ohm IN+ TL1 Zo = 50 Ohm INTL2 R2 84
R3 125
R2 50
R1 50
R4 84
R3 50
OF
RECOMMENDED LAYOUT
REV. D FEBRUARY 11, 2003
www.icst.com/products/hiperclocks.html
10
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
* The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 24 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
X1
GND VCC VIA
U1
PIN 1
C11 C16 VCCA R7 Close to the input pins of the receiver R4 R3 TL1N
TL1N
C15 C14
TL1 R2
TL1 TL1, TL2 are 50 Ohm traces and equal length
R1
FIGURE 6B. PCB BOARD LAYOUT
8430AY-51
FOR
ICS8430-51
REV. D FEBRUARY 11, 2003
www.icst.com/products/hiperclocks.html
11
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-51. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8430-51 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.476W * 42.1C/W = 90C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430AY-51
www.icst.com/products/hiperclocks.html
12
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8430AY-51
www.icst.com/products/hiperclocks.html
13
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430-51 is: 4,534
8430AY-51
www.icst.com/products/hiperclocks.html
14
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc
Reference Document: JEDEC Publication 95, MS-026
8430AY-51
MINIMUM
NOMINAL 32
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0 0.60 0.75 7 0.10 1.40 0.37 0.15 1.45 0.45 0.20
www.icst.com/products/hiperclocks.html
15
REV. D FEBRUARY 11, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8430AY-51 ICS8430AY-51 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS8430AY-51 ICS8430AY-51T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8430AY-51
www.icst.com/products/hiperclocks.html
16
REV. D FEBRUARY 11, 2003

▲Up To Search▲

Price & Availability of ICS8430-51

	To Download ICS8430-51 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .